A Fully-Integrated CMOS Hyperchaotic Map for Obfuscated IoT Communications

This paper describes the analysis and practical integrated circuit (IC) implementation of synchronized hyperchaotic maps for energy-efficient private data communication between (or within) IoT nodes. Either analog or digital data can be obfuscated in the physical layer using chaotic masking and recovered by a synchronized hyperchaotic map at the receiver, resulting in compact and low-power private links that operate independently of the digital processor and do not require additional analog-to-digital conversions. The proposed map was implemented in 180 nm CMOS using fully-differential switched-capacitor (SC) circuits, and a serial peripheral interface (SPI) control interface was added for changing the map parameters (thus allowing post-fabrication trimming and changing of obfuscation keys). The complete system (active die area = 2 mm×1 mm) consumes ~4.5 mW from a 2 V power supply at a clock frequency of 2 MHz. The chip can operate at frequencies up to 6.25 MHz, which results in a link energy efficiency of 4.3 nJ/bit for transmitting analog data with 6-bit precision at a data rate of 3.75 Mbps.