17 GHz transceiver design in 0.13 /spl mu/m CMOS

The paper presents the research work towards a fully integrated 17 GHz transceiver in 0.13 /spl mu/m standard CMOS. The simultaneous challenge of high-integration, highest frequency and low-voltage design is solved combining optimized on-chip passives and RF circuit techniques with a double-conversion sliding RF-architecture. Three measured chips clearly demonstrate the feasibility of a CMOS transceiver at highest frequency. A fully integrated /spl Delta/-/spl Sigma/ 13 GHz PLL consumes 60 mW from 1.5 V supply. The complete RF RX-path features a gain of 37 dB, IIP3 of -37 dBm and an SSB NF of 9.3 dB, consuming 180.8 mW from 1.5 V supply. A first TX path test-chip includes the second modulator and linear output driver. Consuming 93 mW from 1.5 V supply, it features a gain of 4 dB and an OIP3 of 13 dBm.