A Speed-Enhanced Asynchronous SAR Control Logic Based on Two-Phase Handshake Architecture

This paper presents a speed-enhanced asynchronous SAR control logic, based on a two-phase handshake architecture. The control logic comprises of logic cells. Each logic cell employs a static logic gate and an SRAM-latch. The interaction between them, based on a two-phase handshake architecture, supports high-speed output change. The SAR control logic is implemented in a 6b V cm -based successive approximation register (SAR) analog-to-digital converter (ADC) with 1b redundancy in 90 nm bulk CMOS process. Based on the post-layout simulation result, the propagation delay for one bit of conversion by the proposed control logic is 0.24 ns. The power consumed by the SAR control logic is 0.99 mW with 1.2 V supply. The post-layout simulation results for the SAR ADC show an SNDR/SFDR of 36.2 dB and 44.13 dB, respectively at 500 kS/s sampling rate with an input frequency of 54.68 kHz. The simulated differential and integral non-linearity (INL and DNL) are 0.38 LSB and 0.24 LSB, respectively.