A 16/17 prescaler based on novel TSPC 2/3 devider scheme

In this work, new design techniques that aim to reduce power consumption of true single-phase clock-based (TSPC) prescalers is presented. The proposed design technique is applied to a divide-by-2/3 unit, and its performance is compared with previous work to demonstrate the improvement. Simulation results show at least a 49% reduction of PDP is achieved by the proposed unit.