A High-speed H.264/AVC CABAC Decoder for 4K Video Utilizing Residual Data Accelerator

The implementation of a parallel de- coder for CABAC (Context-based Adaptive Bi- nary Arithmetic Coding), which is adopted in the H.264/AVC video coding standard, is extremely diffi- cult due to inherent data dependency. Therefore, the CABAC decoder constitutes a bottleneck when decod- ing 1080 HD (1,920×1,080) or higher video sequences in real time. In this paper, we propose a VLSI (Very Large Scale Integration) architecture for the CABAC decoder that adopts a multi-bin decoding architecture in conjunction with techniques that improve the max- imum clock frequency. The implementation results show that the proposed architecture achieves an aver- age throughput of 1.48 bins per clock and a maximum clock frequency of 394 MHz, demonstrating that our architecture is capable of decoding 4K (4,096×2,048 @ 30 fps) video in real time.