FPGA-based Pre-processing Unit for Real-time Synthetic Aperture Radar (SAR) Imaging

Synthetic Aperture Radar (SAR) is a powerful microwave remote sensing tech- nique which is capable in producing high resolution images from the measurements of the earth surface independent of weather conditions. Range-Doppler algorithm (RDA) is commonly used for the processing of SAR data by massively utilizing Fast Fourier Transform (FFT) and In- verse Fast Fourier Transform (IFFT) operations. The implementation of radix-2 FFT in Field Programmable Gate Array (FPGA) is presented in this paper. This paper highlights the design and development of a FPGA-based pre-processing unit for real-time SAR imaging. Particu- larly, an e-cient FFT processing module has been developed. The proposed architecture signifl- cantly reduced the hardware resources while achieving the reasonably high processing speed and throughput rate. 1. INTRODUCTION Radar was originally developed for the purposes of military during World War II. The initial purpose of radar was to track ships and aircrafts through darkness and heavy weather. It has experienced a steady growth, with advances in radio frequency (RF) technology, antennas, and more recently, digital technology (1). According to Carl Wiley (2), Synthetic Aperture Radar (SAR) was flrst proposed in 1951 which described the use of Doppler frequency analysis in order to improve the radar image resolution. With the radar system mounted on a ∞ying platform (e.g., UAV), the forward motion of the actual antenna is used to synthesize a long antenna. This allows the use of longer wavelengths and still capable to achieve good resolution with reasonable antenna structures and size. Range-Doppler algorithm (RDA) is one of the image formation techniques which commonly used in processing the collected SAR data into an image. Figure 1 shows the functional block diagram of the RDA. The main purpose of SAR imaging system is to achieve elevation and azimuth pulse compression. These compressions are done by the range-Doppler algorithm which is designed to achieve block processing e-ciency, using frequency domain operations in both range and azimuth, while maintaining the simplicity of one-dimensional operations (3). The algorithm starts with the range compression in which a range FFT is performed followed by a range matched flltering multiplication. Figure 2 shows the range compression in frequency domain by making use of FFT and IFFT. After the multiplication of matched flltering, a range IFFT is performed in order to complete the range compression. Once the range compression is done, an azimuth FFT is carried out in order