Critical charge model for transient latch-up in VLSI CMOS circuits

Experimental results and theoretical considerations on the critical charge model for latch-up in VLSI CMOS circuits are presented. The critical charge is constant, proportional to the trigger phase pulse height, and inversely proportional to the trigger pulse width. With these results it is possible to calculate the transient latch-up susceptibility of circuits due to periodic pulses, e.g. overshoot, undershoot, and glitches. >