A process for preparing Doppelgate- and tri-gate transistors with independent access in the same process flow as well as an integrated circuit this comprehensive

A method comprising: Forming at least two silicon bodies (15, 16) with the overlying insulating members (17, 18); Forming a sacrificial layer over the silicon bodies with overlying insulating members; Patterning the sacrificial layer, said gate regions (20, 22) are defined, which cross the silicon body (15, 16); Surrounding the patterned sacrificial layer and the silicon body (15, 16) with the overlying insulating members (17, 18) with a dielectric layer (30), so that the insulating members (17, 18) are exposed, Covering one of the insulating elements (17) for protection against etching; Etching the other insulating member (18) while an insulating member (17) covers; Removing the patterned sacrificial layer without removing the dieletrische layer (30); Forming a gate insulating layer (60) and gate metal layer (61) within the gate regions.