A 55nm logic process compatible p-flash memory array fully demonstrated with high reliability

A high-density p-Flash macro compatibly integrated in a 55nm LL (Low Leakage) logic process is well designed with novel low power high speed architecture and fabricated in this paper. Moreover, it is demonstrated that the p-Flash macro is fully functional with good performance and solid endurance reliability at commercial temperature range. This p-Flash memory technology can widely be embedded in different application platforms such as IoT application, mobile computing, mobile storage, MCU application, smart card and can continually be scaled to 28nm or even more advanced technology nodes without sacrificing performance and reliability.