17.4 A 14nm 1.1Mb embedded DRAM macro with 1ns access

IBM introduced trench capacitor eDRAM into its high performance microprocessors beginning with 45nm and Power 7 [1] to provide a higher density cache without chip crossings. Whereas the 45 and 32nm designs employ a micro sense amplifier [2] and three-level bitline hierarchy, the design implemented for 22nm utilizes a higher gain sense amplifier and two-level bitline architecture that together provide significant reductions in area, latency, and power. This 22nm design style has been migrated into a 14nm FinFET [3] learning vehicle, complete with an ABIST engine, wordline charge pumps (VPP and VWL), and padcage interface circuitry.