Post-Placement Optimization for Thermal-Induced Mechanical Stress Reduction

This paper presents a post-placement technique for through-silicon-via (TSV) induced thermal mechanical stress reduction. Thermal mechanical stress causes several critical failures such as material fracture (interfacial delamination and silicon substrate cracking) and TSV stress migration (SM). The von Mises stress is used as a material fracture metric. An analytical TSV SM model is used, which replaces time-consuming finite-element-method (FEM) based simulation. The von Mises stress criterion and the analytical SM model are combined to form a unified placement optimization problem to alleviate both material fracture and SM problems. Considering the TSV-induced thermal mechanical stress profile strongly depends on TSV placement and thermal profile, iterative optimizations are performed to optimize the placement of TSVs and power-dissipating gates. Results show that compared to an initial reliability-unaware 3D placement, our design achieves 2.44x longer SM mean-time-to-failure (MTTF), 23% reduction in von Mises stress, with only 3% wirelength overhead.