Low-Complexity and High-Speed Architecture Design Methodology for Complex Square Root

In this paper, we propose a low-complexity and high-speed VLSI architecture design methodology for complex square root computation using COordinate Rotation DIgital Computer (CORDIC). The proposed methodology is independent of angle computation in the CORDIC unlike the state-of-the-art methodologies. The proposed methodology is modelled in VHDL and synthesized under the TSMC 45-nm CMOS technology @ 1 GHz frequency. The synthesis results show that the proposed design saves 18.39%, 4.06% and 17.26%, 2.56% on chip area and power consumption when compared with the state-of-the-art methodologies without loss in accuracy. The proposed design saves the latency of 16 and 14 clock cycles when compared with the state-of-the-art implementations. The proposed design can process 23.4 and 127.344 billion additional samples per one joule energy when compared with the state-of-the-art designs.