New stress voiding observations in Cu interconnects

Stress voiding (SV) in Cu vias and lines is investigated on 300 mm wafers after storage at temperatures ranging from 175/spl deg/C to 400/spl deg/C. Sensitivity to SV in lines decreases with metal pattern density. Microstructural analysis of Cu lines shows that voids are not only found at grain boundaries, but also within the grains, indicating bulk and/or surface diffusion of vacancies. Via resistance increase well above 10% is observed. Both via and line SV is observed below and above zero-stress temperature, indicating two mechanisms: vacancy diffusion in combination with tensile stress, and Cu densification under compressive stress. SEM and pattern recognition observations on Cu lines are presented. Line void volume distribution is lognormal, while the distribution of the increase in via resistances is bimodal.