Method of manufacturing integrated circuit comprising vias passing through the substrate

The invention relates to a method of forming an integrated circuit, comprising the steps of: forming electronic components on a first face (10f) of a substrate (10); forming a stack of interconnect levels (14) on said first face (10f), each interconnection level comprising conductive tracks (40) separated by an insulating material (42); forming at least one hole (26) from a second face (10b) of the substrate (10), the hole stopping on one of the conductive tracks (40); depositing on the walls and the bottom of the hole, a conductive layer (28) and fill the remaining space with a filler material (30); and forming, in an interconnection level or surface of the interconnect stack (14), and opposite the hole, at least one region (50) of a material having a 50 GPa elastic modulus and elongation to greater than 20% disruption, isolated from the conductor tracks (40).