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Development of verification and power estimation methodology for circuits with Run Time Power Gating
Development of verification and power estimation methodology for circuits with Run Time Power Gating
2008
Nakata Mitsutaka
Shirai Toshiaki
Kashima Toshihiro
Takeda Seidai
Usami Kimiyoshi
Seki Naomi
Hasegawa Yohei
Amano Hideharu
Keywords:
Power gating
Dissipation
Electronic circuit
Computer science
Electronic engineering
Correction
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