High-Order Frequency-Locked Loop: General Modeling and Design

To improve the filtering capability of frequency-locked loop (FLL), the high-order bandpass filters FLL was proposed recently. This paper proposes a high-order FLL in synchronous (dq) reference frame where the high-order lowpass filter is adopted. A general analytical model is established for the high-order FLL. Based on the model, it is proven that the conventional high-order FLL exhibits no improvement in terms of filtering ability of the frequency estimation. Based on this analysis, a new frequency estimation loop is proposed to obtain an enhanced filtering capability for the FLL. Additionally, the proposed high-order FLL has the advantage of simple implementation compared to conventional high-order FLLs. A design example is then demonstrated and simulated to show the accuracy of the model and the effectiveness of the proposed FLL. Finally, the proposed high-order FLL is experimentally verified on a testbed using a 32-bit floating-point DSP TMS320F28379D at 200 MHz.