A basic study on chip size determination of MOSFETs to minimize total power loss

Chip area of power semiconductor devices is one of the key parameters to realize highly-efficient converters. In the case of MOSFETs, a larger chip area results in lower on-state resistance. However, switching loss and gate drive loss may become dominant due to increase in parasitic capacitances when the chip area is too large. Thus, the chip area must be determined adequately considering given operating conditions and characteristics of the devices. In this paper, relationship between the chip area and loss reduction effect in three different types of MOSFETs, that is, silicon MOSFETs, silicon-carbide MOSFETs, and super-junction MOSFETs, is investigated experimentally. From the results, it is clarified that each MOSFET has the optimum points of the chip area for the loss reduction depending on the switching frequency and current. A determination criterion of the optimum chip area is discussed on the basis of the theoretical calculation of the losses.