낮은 트리거 전압 기술을 이용한 MOSFET 기반 ESD 보호회로의 특성 비교에 관한 연구

Electrostatic discharge (ESD) damage has become the main reliability issue for deep-submicron CMOS integrated circuit. This paper presents comparisons of ESD protection circuits using low trigger techniques in a 0.13 um CMOS process, Transmission line pulse (TLP) and human body model (HBM) results support the findings presented in this paper.