The modified P+ electrode layout schemes to enhance esd robustness of SCR structure for PMIC applications

In this work, the MPSCR structure have been verified in a 0.35-um 40-V CDMOS technology. The MPSCR structure with high ESD robustness has been clearly investigated by TLP instrument and TCAD simulator. By the simulation results, the modified P+ electrode layout of cathode side can enhance the turn-on efficiency of embedded SCR path, and avoid the current crowding effect on the surface of device. The proposed device only need to sweep N+ and P+ regions in drain side, and do not need to increase the additional mask layer. For area reduction, the MPSCR device does not need to increase the layout area and it can sustain up to 7.2kV for HBM and 360V for MM under device width of 300µm. Besides, the proposed MPSCR device has a low trigger voltage (Vt1=54-V) and a high second breakdown current (It2=10-A), which can be extensively applied for ESD protection design of PMIC applications.