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Power Analysis against a FPGA Implementation of the AES with SubBytes in a memory table
Power Analysis against a FPGA Implementation of the AES with SubBytes in a memory table
2008
Kawakita Hiroyuki
Nishimoto Yusei
Ishikawa Kiyohiko
Imaizumi Hiroyuki
Keywords:
Field-programmable gate array
Power analysis
Embedded system
Computer science
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