Biquad implementation of an IIR filter for IQ mismatch correction in an SoC RF receiver

This paper presents an IQ mismatch correction design and implementation that is part of a system-on-chip (SoC) that also includes a homodyne RF receiver and a sparse nonlinear equalizer. It uses IIR filters to help the RF receiver achieve greater than an 80 dB image rejection ratio. The IIR filters are implemented using biquad structures to minimize power consumption by limiting the number of bits used per tap. The design was implemented in 65 nm CMOS technology and it is estimated to have a power performance of 150 GOPS per watt.