Synthesis of Multivalued Logical Networks for FPGA Implementations

This paper presents the method of FPGA-oriented synthesis of multiple-valued logical networks. Multiple-valued network consists of modules connected by multiple-valued signals. During synthesis each module is decomposed into smaller ones, that may be implemented using one logic cell. For this purpose the symbolic decomposition is applied. Since the decomposition of modules strongly depends on encoding of multivalued inputs and outputs, the result of synthesis depends on the order, in which the consecutive modules are implemented. In our approach we optimize this order using developmental genetic programming. Experimental results showed that our approach significantly reduces the cost of implementation.