Double-Gate Junctionless 1T DRAM With Physical Barriers for Retention Improvement

In this article, a double-gate (DG) junctionless (JL) transistor with physical barriers is proposed for one-transistor dynamic random-access memory (1T DRAM) application. In this topology, the holes are stored in the region blocked by physical barriers constructed by oxides underneath the source and drain regions rather than a potential well formed by n+-p-n+ as in the conventional structures. The proposed topology achieves an elongated retention time ( ${T}_{\text {ret}}$ ) with larger physical barrier thickness ( ${T}_{\text {oxPB}}$ ) and wider barrier offset length ( ${L}_{\text {BO}}$ ) due to a reduction in band-to-band tunneling (BTBT) (during hold “0”) and recombination (during hold “1”). Maximum retention times of ~2.5 s and ~33 ms have been achieved for channel doping of 1019 cm−3 at 27 °C and 85 °C, respectively, with gate length ( ${L}_{g}$ ) of 100 nm at small drain bias ( ${V}_{\text {DS}}$ ) of 1 V during write “1.” Results demonstrate a better gate length scalability and a retention time of ~4 ms at ${L}_{g}$ of 15 nm with thinner Si channel thickness under the gate ( ${T}_{\text {Si}}$ ) and thicker ${T}_{\text {oxPB}}$ . In addition, the effect of temperature on retention time has been analyzed. With optimized ${T}_{\text {oxPB}}$ at ${L}_{g} = {100}$ nm, the retention time decreases due to thermal generation and recombination from ~2.5 s at 27 °C to ~3 ms at 125 °C.