GIDL simulation and optimization for 0.13 /spl mu/m/1.5 V low power CMOS transistor design

In this work, we calibrate a BTBT model based on measured GIDL data, and incorporate the model into our process/device simulations to directly correlate process with device performance and leakage. For the first time, we quantitatively explore an overall picture of tradeoffs between device leakage and performance as functions of process conditions. The explored design space has been used in process optimization for our 0.13 /spl mu/m/1.5 V low power (LP) CMOS transistors. We demonstrate that such predictive TCAD simulations to determine and optimize process conditions can effectively reduce development time and cost. We describe GIDL mechanisms in our 0.13 /spl mu/m/1.5 V LP transistors, and explain, via simulations, that the measured GIDL current manifests different IN behaviors depending on whether the dominant BTBT location is at the gate oxide/Si interface or below in the Si bulk.