Old Web
English
Sign In
Acemap
>
Paper
>
An Experiment Design for Measuring Response Time of FPGA Logic Cell
An Experiment Design for Measuring Response Time of FPGA Logic Cell
2018
Zhou Huanyin
Xu Mei
Hu Jiewei
Xie Yanhui
Lv Ziyong
He Gaokui
Keywords:
Field-programmable gate array
Computer hardware
Design of experiments
Response time
Computer science
logic cell
Correction
Source
Cite
Save
Machine Reading By IdeaReader
0
References
0
Citations
NaN
KQI
[]