Modeling of gain in advanced CMOS technologies

L and ∆W extraction The impressive downscaling of CMOS technology and its more and more massive introduction in System-on-Chip (SoC) oriented applications require a modeling approach able to describe new physical effects paying attention to such different environments (digital and analog) coexisting in a single technological platform for SoC. In particular, in this paper we deep insight the modeling of gain, a key parameter ruling the analog performances in relation with their layout dependence affected by the shallow trench isolation (STI) induced mechanical stress. Both n- and p- channel have been investigated as a function of temperature. The W scaling modeling has been dealt with for the first time. A 90 nm CMOS advanced technology for Embedded Flash applications has been characterized.