A New Vertical Channel LDMOS

A new vertical channel LDMOS, which decreases the on-resistance without sacrificing the breakdown voltage, is proposed and verified by numerical simulation. In the proposed vertical channel LDMOS, the channel and the drift region are located in the trench between the source and the drain. The total cell pitch of the proposed device is decreased to 4 μm which is about a half of the conventional LDMOS when the breakdown voltage is 60 V. Simulation results show that the on-resistance is 0.45 mΩ cm2 for a 60 V breakdown voltage which is very low compared to that of the conventional LDMOS.