Investigation of the characteristics of GIDL current in 90nm CMOS technology

A specially designed experiment is performed for investigating gate-induced drain leakage (GIDL) current in 90nm CMOS technology using lightly-doped drain (LDD) NMOSFET. This paper shows that the drain bias VD has a strong effect on GIDL current as compared with the gate bias VG at the same drain–gate voltage VDG. It is found that the difference between ID in the off-state ID−VG characteristics and the corresponding one in the off-state ID−VD characteristics, which is defined as IDIFF, versus VDG shows a peak. The difference between the influences of VD and VG on GIDL current is shown quantitatively by IDIFF, especially in 90nm scale. The difference is due to different hole tunnellings. Furthermore, the maximum IDIFF(IDIFF,MAX) varies linearly with VDG in logarithmic coordinates and also VDG at IDIFF,MAX with VF which is the characteristic voltage of IDIFF. The relations are studied and some related expressions are given.