A CMOS Digital PLL with a New Phase-frequency Detection Technique

A low-power digital phase-locked loop(DPLL) based on a new digital phase-frequency detection technique is presented. Compared with the traditional charge-pump PLL, the proposed DPLL eliminates phase “dead zone” and has the advantages of fast-locking, low-jitter, low-power, and a wide locking range. The DPLL works from 60 MHz to 600 MHz with a maximum power consumption of 3.5 mW at a supply voltage of 1.8 V. It also features a fractional-N synthesizer with digital 2 nd -order sigma-delta noise shaping, which can achieve the small step size and improve phase-noise spectrum. The DPLL has been implemented in a 0.18 μm quintuple-metal CMOS process. The peak-to-peak jitter is less than 0.5% of the output period( T out ), and the lock time is less than 150 times of the reference clock period after the predivider( T pre )