Design and Simulation of Low-power Conditional-Discharging Flip Flop

In this seminal, a low-power conditional discharging-flip flop (Modified CD-FF) has been presented. A clock-pulse by single feedback through scheme is proposed for use in the Modified CD-FF. Two inverters in clock-pulse generator circuit have been removed to optimize delay in clock path. In this low-power circuit design, the clock pulse is designed by a single inverter and pass-transistor logic (PTL). The proposed circuit (MCD-FF) reduces the additional switching activity of certain internal nodes as well as generates less glitch in the output with a lesser transistor count. As a consequence, the width of transistor is increased to manage the delay for clock pulse. Overall performances of circuit design provides better optimized area, delay and power consumption (average power) than earlier flip flop designs compared to 90nm technology.