A frequency-domain high-speed bus signal integrity compliance model: Design methodology and implementation

This paper investigates channel/link frequency domain compliance in order to predict compatibility with a bus's chip I/O circuitry at its ends. Any channel can be associated with certain frequency domain parameter values which are easily calculated from the channel S-parameter matrix. A set of frequency domain parameters that can sufficiently describe a channel are defined in this paper. Using a genetic algorithm, the frequency domain parameter bounds in a multidimensional space describing PCIe-Gen3 (bus speed = 8 Gb/s) compliant channels are found. Details of the methodology used in order to arrive at the multidimensional frequency domain compliance model, model results and model simulation validation testing are presented.