A SRAM Bitcell Design for Ultra-Low Supply Application

This paper presents a novel SRAM bitcell structure which is applied for ultra-low voltage. The bitcell is composed of 8 transistors, two additional NMOS transistors in series is added to traditional 6T structure as a read out port. Besides, the back to back to inverter is designed by high threshold voltage transistors. Simulations in simic 130 nm process are operated. The simulation results show that the hold and read static noise margin of proposed bitcell have enhanced greatly comparing to conventional 6T, additionally, this new bitcell can operate correctly in ultra-low voltage region. Comparing to conventional 6T cell, the static power consuming of this bitcell is reduced by 60%~70% in low voltage region.