A High Throughput Power-Efficient Optical Memory Subsystem for Kilo-Core Processor

High throughput and power-efficient processor-memory communications are of great importance for kilo-core processor design. This paper proposes a hybrid photonic architecture for such communications. Bandwidth-efficient photonic burst switching is used for memory accesses between last-level HBM caches and off-chip HMC memory pools. Simulation results show that the hybrid network achieves up to 25% of system speedup and up to 10 times of energy savings, when compared to conventional electric interconnects.