Electrically erasable programmable read-only memory

The present invention discloses an electrically erasable programmable read only memory, comprising at least: a semiconductor substrate; on the semiconductor substrate spaced from heavily doped N-type source region and drain region and channel region of the channel region located between the source region and the drain region; first bit line and second bit lines respectively connected to the source region and the drain region; a first floating gate disposed on the channel region and the source the upper region, a second floating gate disposed over the channel region and the drain region, the first floating gate and the second floating gate respectively constitute a first and a second memory bit cells storing a bit cell; a first control a second gate and the control gate, respectively disposed on the top of the first floating gate and the second floating gate; and a word line, located above the channel region and floating gate positioned between the first and second floating gate, the present invention, avoids the extensive use of the word line voltage selection switch, reducing the area of ​​the chip.