Comparative analysis on low power SRAMs

Abstract Static Random Access memory (SRAM) has become an important role due to their low access time and storage capacity. The Static Random Access Memory (SRAM) has a significant impact on the overall power consumption and energy efficiency. The leakage power in SRAM is one of the most significant problems when technology node is scaling down. The main concept of this survey is to compare various Low power SRAMs based on their power consumption as well as delay in the SRAM. Different types of power reduction techniques like power gating, sleepy keeper leakage control transistor technique (SK-LCT), Gated ground sleep logic, LECTOR and MTCMOS techniques, etc.. are applied to the SRAM to reduce the power consumption and various parameters like leakage power, delay, speed and Static Noise Margin (SNM) in different EDA tools like Tanner, Cadence, Silvaco TCAD etc., This comparative analysis conclude that forced sleep technique is reduces power consumption and up to 40% and 43% respectively when compared with other technique. This comparative analysis helps the designer and researchers to get the overview of all the available techniques with their results, so they can choose the best techniques based on their specific requirements.