3D VLSI: A Scalable Integration Beyond 2D

As the semiconductor industry faces serious challenges extending the CMOS roadmap, traditional cost reduction benefits that accompanied power/performance/area (PPA) advantages of successive technology nodes have decreased due to a myriad of process integration challenges and increased variability, reliability, power and thermal constraints. 3D integration technologies have been pursued as a potential solution to help integrate more functions within a confined available dimensions of advanced mobile devices. 3D VLSI (3DV) is an emerging 3D integration technology that unlike packaging-driven 3D technologies (e.g., 2.5D, TSV-based 3D, etc.) can deliver orders of magnitude more integration densities due to extremely small sizes of vertical vias. In this paper, we describe the 3DV technology and its current benefits and challenges. We also survey recent literature that show the potential of 3DV to help continue Moore's law trajectory beyond 2D.