A shared hard decisions storing in partially parallel FPGA-based QC-LDPC decoder

A strategy of hard decisions sharing intrinsic and extrinsic memory banks for partially parallel Quasi-Cyclic (QC) LDPC decoder is proposed in this paper. The proposed method not need extra memory banks to store hard decisions, could reduce the total number of memory by 33% compared with the decoder in reference [6] which is significantly fewer memory banks than the other published FPGA implementations decoders in reference [4–8], while maintaining the same hardware requirements at the same throughput level.