Tough Bugs vs. Smart Tools - L2/L3 Cache Verification Using System Verilog, UVM and Verdi Transaction Debugging

Verdi's Transaction Debug helps record, visualize, analyze and debug transactions at higher level of abstractions. With recorders integrated inside the Verdi UVM libraries and convenient Verdi APIs, UVM sequences and user-level transactions are recorded automatically and available for debug. In this paper, we discuss some of L2/L3 SV/UVM test scenarios and how Verdi Transaction Debug was used to model and debug out-of-order transactions. For example, in a cache miss scenario, L3 forwards the request to external bus where four responses are fetched out of order. Using Verdi APIs, Centaur modeled the request as a Parent Transaction and the four Responses as Children Transactions. Verdi Transaction Debug was then used to quickly find the linked parent (Request) - children (Responses) transactions, which were spread across hundreds of clock cycles, by highlighting the related transactions. This allowed for quickly debugging failing tests due to missing responses or unfinished transactions.