Recent advances in low temperature process in view of 3D VLSI integration

C. Fenouillet-Beranger,P. Batude,L. Brunet,Vincent Mazzocchi,C.-M. V. Lu,F. Deprat,J. Micout,M.-P. Samson,B. Previtali,P. Besombes,N. Rambal,V. Lapras,F. Andrieu,Olivier Billoint,Melanie Brocard,Sebastien Thuries,G. Cibrario,P. Acosta Alba,B. Mathieu,S. Kerdiles,Fabrice Nemouchi,C. Arvet,P. Besson,V. Loup,R. Gassilloud,X. Garros,C. Leroux,Virginie Beugin,C. Guerin,D. Benoit,L. Pasini,J.-M. Hartmann,M. Vinet

Recent advances in low temperature process in view of 3D VLSI integration

2016

In this paper, the recent advances in low temperature process in view of 3D VLSI integration are reviewed. Thanks to the optimization of each low temperature process modules (dopant activation, gate stack, epitaxy, spacer deposition) and silicide stability improvement, the top layer thermal budget fabrication has been decreased in order to satisfy the requirements for 3D VLSI integration.

Keywords:

Logic gate
Annealing (metallurgy)
Very-large-scale integration
Epitaxy
Thermal stability
Silicide
Electronic engineering
Dopant Activation
Materials science
Fabrication
Nanotechnology
Engineering physics

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