Maximizing ESD robustness of current-mode-logic (CML) driver with internal gate bias network

In this paper the ESD robustness of Current-Mode-Logic (CML) drivers with various gate bias configurations is first investigated to find an optimized bias condition. Circuit simulations with integrated ESD shell models are also performed to compare with the experimental data. Based on the experimental and simulation results, an internal ESD network is then proposed to bias the gates of transistors in CML driver to the optimized condition during an ESD event and to maximize the ESD protection performance.