A novel technique for p-well NMOS power ICs

A novel technique is proposed for the design and fabrication of p-well NMOS power integrated circuits (PICs). Theoretical analysis and experimental results show that p-well NMOS ICs can be compatibly integrated with VDMOS cells in one chip, and butt joint lateral diffusion-obtained p-n junctions have the same breakdown properties as commonly diffused ones. As an example, considerations on the layout design of the PIC structure are given.