Contact block architectures for transistors having channels in a nano-order and method of forming

Device comprising: a plurality of parallel semiconductor bodies, each of said plurality of parallel bodies having a top and a pair of laterally opposite sidewalls, each of said parallel bodies having a channel portion between a source region and a drain region; a gate electrode formed adjacent to and above the channel region of each of the plurality of body; a first metal source or drain contact that is connected to a first plurality of said plurality of parallel bodies and extending between these on a first side of the gate electrode; a second metal source or drain contact that is connected to a second plurality of said plurality of parallel bodies and extending between these on the first side of the gate electrode; and a third metallic drain or source contact, which is connected to the first and second plurality of the plurality of parallel body and extending between these on a second side of the gate electrode.