Thermal-Aware Floorplanner for Multi-core 3D ICs with Interlayer Cooling

Internal thermal problem has become a critical challenge in multi-core 3D ICs. The interlayer cooling system provided a new solution for this problem, and expanded the design space of multi-core microprocessor floorplan. This work proposes a thermal-aware floorplanner for multi-core 3D ICs with interlayer cooling, with iterative algorithm based on simulated annealing method. The results show that the maximal temperature is reduced by 15\(^{\circ }\) C, and the temperature gradient is reduced by 28.4\(^{\circ }\) C compared to the baseline design with 3 active device layers.