Application of the layout-aware single event simulations to a design of 65 nm memory units

This paper reports about an application of our technique to the actual design procedure of the single event effect tolerant 65nm SRAM and register file cells, which are based on DICE and 6T cells. The technique is integrated to a design flow, accepted in our department. Input data for the analysis is layout and circuit designs of the cells. Layout design from later stages of the cells design flow is used. Output data are cross section plots and upset multiplicity maps.