Evaluation of Latch-Based PUFs Implemented on 40 nm ASICs

Physical Unclonable Function (PUF), an anti-counterfeit technology for semiconductor chips, has come under focus in recent years. We proposed a method of enhancing the entropy of a latch-based PUF response and confirmed its effectiveness by experimenting with prototype latch-based PUFs for 180 nm CMOS ASICs. In this paper, we fabricated latch-based PUFs implemented on 40 nm CMOS ASICs and assessed the basic performance and the effectiveness of the proposed method. The results show that the response error rate remains 15% or less at varied temperatures (-20 – 85 degrees Celsius) and voltage (1.10 V within plus or minus 10%) while maintaining high robustness. We confirmed that the response entropy of the PUF made of 256 latches increased from 178 to 233 bits. These results show the effectiveness of the proposed method when the latch-based PUF is fabricated in the 40 nm CMOS process. In comparing assessments of the latch-based PUF of the 40 nm and 180 nm processes (previous results), the latch-based PUF is expected to be less dependent on the manufacturing process.