Non-Visual Defect Monitoring with Surface Voltage Mapping

Non-Visual Defects (NVD) is a category of semiconductor material and process induced defects that cause electrical failures, but are not detected with visual wafer inspection tools. This paper gives an overview of our non-contact electrical NVD metrology that uses fast whole wafer inspection with standard mm resolution Kelvin probe surface voltage mapping. In an advanced approach detected NVDs are mapped in high resolution (μm range) using Force Kelvin Probe Microscopy. In depth NVD characterization is done with the corona-Kelvin method that quantifies dielectric and interfacial properties in the defect site. This characterization is performed in a non-invasive fluence range of corona charging and all measurements are non-contact, and do not require fabrication of test devices. A broad application range is demonstrated with examples relevant to silicon IC, silicon photovoltaics and to wide bandgap epitaxial SiC. © The Author(s) 2015. Published by ECS. This is an open access article distributed under the terms of the Creative Commons Attribution Non-Commercial No Derivatives 4.0 License (CC BY-NC-ND, http://creativecommons.org/licenses/by-nc-nd/4.0/), which permits non-commercial reuse, distribution, and reproduction in any medium, provided the original work is not changed in any way and is properly cited. For permission for commercial reuse, please email: oa@electrochem.org. [DOI: 10.1149/2.0161604jss] All rights reserved. Wafer inspection based on surface voltage mapping is used in silicon IC processing for detection of a broad category of defects that are revealed on the surface as localized regions with different values of surface potential. The approach has been very successful in monitoring of plasma etch damage 1‐3 and was also applied to ion implant, 4,5 and wet etch process monitoring. 6 Localized charging of the silicon wafer by unbalanced plasma or an ion beam can lead to localized melting due to arcing. In less extreme cases, charging can causeantennadamagetothegatedielectric.Itcanalsoattractparticles increasing surface contamination. The root cause of these electrical defects is the charging of the surface by a process that is not detected by optical based inspection tools.Whenthefailureoccursitisnoteasytotroubleshoottheproblem since at a later stage only the consequence of charging, but not the charging itself, is being detected. In addition to surface charge, there are other process related defects not revealed by optical inspection. In 2009 ISMI has defined non-visual defects (NVD) as a novel category of defects (novel in their classification) that cause electrical failures but do not leave behind a physical remnant that can be affordablydetectedwithvisualwaferinspectiontools. 7 CommonNVDsalso includesurfacemetalcontaminants(Cu,Fe);alkalimetals(ionsNa + ); and gate metal effective work function defects. In this overview we include historically important examples of surface voltage mapping, dating back to mid 1990’s. Significant refinement of the technique and the improvement of map resolution and measurement speed have only recentlybeenintroduced,usingmultipleKelvinprobesinanovelgeneration of surface voltage mapping, SVM tools. 8 The corresponding most recent application examples include monitoring of defects in Si patterned wafers and high resolution intra-die mapping with microKelvin Force Probe. 8 Finally, we discuss extension of the technique to epitaxial SiC layers and we compare surface voltage mapping of defects with mapping of lifetime degrading defects. 9,10 The corresponding SiC results illustrate three stages of our metrology: 1-whole wafer defect mapping; 2-defect identification with high resolution Kelvin Force Microscopy mapping and 3- further defect investigation using DLTS-like surface voltage transient analysis. For certain applications the surface voltage NVD metrology uses surface charge biasing performed with corona charging. Noninvasive