Low size FFT core for OFDM communications

In this work two FFT architectures to be used in a ISDB-T OFDM modulator are presented. The proposed architectures are based in the Radix algorithm. In particular, a radix-2 and a radix-4 are implemented. The main objective is to achieve a very small footprint, in terms of the resources/space demanded by the core, keeping the performance of the standard FFT cores used as ISDB-T OFDM modulator, which will be the final use of the core. Radix algorithm has been selected because it provides high re-utilization, implemented over an iterative structure, using only one design of a butterfly module, multiplier and memory. In this scheme, the main complexity is in the control unit and the datapath. The FFT core is described using the Verilog hardware description language and the test scripts were written in the Matlab script language.