Design of Low Power VLSI Architecture of Line Coding Schemes

Line coding is used to tune the wave form based on the properties of the physical channel. The wave form is tuned in voltage or current or photon levels for the proper digital data transport. Bi-Phase Mark Coding (BMC), Bi-Phase Space Coding (BPSC) and Phase Coding (PC) are used as Line coding techniques. Most of the existing systems discuss about any one of the coding techniques among BPSC and PC. Limited number of systems discusses about BPSC and PC generation and degeneration operations together. The first objective of the proposed work is to design BMC, BPSC and PC techniques Generation and Degeneration operation in a single system. The second objective is to reduce the area and power consumption by modifying the number of MOS devices used for the system design and by adjusting the width of the MOS devices. The system is designed using Cadence® Virtuoso Schematic Editor at 180 nm technology. Simulation is done using Cadence® Virtuoso ADE and the Layout is designed using Cadence® Virtuoso Layout Suite XL. The proposed system requires 59 transistors and occupies 1632.88 µm2. Required power can be reduced up to 33% by using any one of the suitable coding among BMC, BPSC and PC based on the properties of the input data signal. If the input data is having equal possibility of high and low level signals, PC technique will be suitable for power reduction. If the high level beats the low level, BPSC technique will be suitable. If the low level beats the high level, BMC technique will be suitable.