Low Warpage Wafer Level Transfer Molding Post 3D Die to Wafer Assembly

In the broad-spectrum of 3D system integration technologies, stacking of die at wafer level is considered a promising and cost effective platform solution for 3D device and 2.5D interposer assembly. The 3D die-to-wafer (D2W) approach consists of a sequence of processes: D2W stacking, wafer-level die encapsulation ("wafer reconstruction") using e.g. wafer-level molding, Wafer thinning, Through Silicon Via (TSV) reveal and backside passivation, and finally the addition of a redistribution layer (RDL) and bumping or wafer level solder ball attach. The area explored in this paper is the 300mm wafer molding after D2W attachment. A major concern with this approach is the typically large wafer warpage after wafer level molding. This makes post-processing of the reconstructed wafers difficult with standard semiconductor equipment. Typical warpage after wafer molding of 775µm thick silicon combined with equal thickness of 775µm moldcap is around 8 mm. This is due to the large mismatch in coefficient of thermal expansion (CTE) between the materials. As a result of this large warpage, bonding the reconstructed wafer to a special carrier substrate is required to further process the wafers. This requires additional bonding and debonding equipment as well as several additional processing steps with low added value. In this paper, we will describe two different options to reduce the wafer warpage post molding. The first option is the transfer molding with exposed die. Exposed die molding reduces the amount of mold material as there is no mold compound on top of the die. It will be shown this can effectively reduce the substrate warpage to less than 1.5mm for 300mm diameter wafers. The exposed die configuration can also be used in high power application since heat sinks can be directly attached to the die backside. The second option is the transfer molding of the D2W stack together with an additional balancing wafer. The mold material is injected in a cavity formed by the stacking of the D2W and the balancing wafer. After molding, the resulting wafer warpage of the composite "D2W/W" stack is well below 200µm, compatible with semiconductor process equipment. Also important to note is the temperature independence of the warpage of this balanced stack construction. As in this approach, we can realize a direct contact between the stacked die and the balancing wafer, the balancing wafer will also act as a package-sized heat spreader. In this paper, the feasibility of Wafer Level Packaging using the transfer molding method of D2W assemblies will be demonstrated for thin mold cap, exposed die and balancing wafer approaches. The obtained experimental results are used to validate a theoretical model for predicting wafer warpage post wafer molding.