A 1.2V 30nm 1.6Gb/s/pin 4Gb LPDDR3 SDRAM with input skew calibration and enhanced control scheme

Mobile DRAM is widely adopted in battery-powered portable devices because of its low power. Recently, in mobile devices such as smart phones and tablet PCs, higher performance is required to support 3D gaming mode and high-quality video. These trends lead to consideration of higher-performance DRAMs than LPDDR2, while the power budget for DRAMs for mobile devices cannot increase. DRAMs with wide I/O or serial I/O have been reviewed as candidates for over 6.4GB/s channel bandwidth. However, wide-I/O DRAMs [1] must solve issues such as stacking yield for higher density and failure analysis modeling of sys-tem-in-package (SiP), and most serial I/Os have worse I/O power efficiency than LPDDR2. For an evolutionary successor of LPDDR2, therefore, we design a 1.2V 1.6Gb/s/pin ×32 4Gb low-power DDR3 SDRAM (LPDDR3) with input skew calibration and enhanced refresh control schemes, achieving 6.4GB/s total data bandwidth. Most features of LPDDR3 are backward compatible with LPDDR2, except that channel termination, command-address (CA) training, and write leveling are adopted.